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Imagine for example that the isolation cell has one mvrc synopsys its inputs protected with a high Vt implant to better withstand the fluctuations of a floating input from the off island.

MVRC (Multi Voltage Rule Check)

Such a cell property needs identification. Tools hence need to understand this property and check for its correct realization in the design.

Another example is when the isolation enable is inverted in the cell. Not only should we not mvrc synopsys the data input to this pin thereby causing an un-isolated input internal to the cellbut also, this information must be factored into synthesis, static and verification.

Cells with multiple rails such as power switches, level shifters, charge pumps etc.

It is also typical to enclose a function attribute into traditional representations. Power management cells make this mvrc synopsys, because sometimes the function may be quite mixed-signal-like in its behavior.

It must be recognized therefore, that certain cells may not have mvrc synopsys right functional model.

Further, their simulation models must be built with care. It is a matter of debate whether the power and ground mvrc synopsys of a cell must be included in the simulation models.

  • Low-Power Design
  • Which tools can accept the same UPF?
  • MVRC (Multi Voltage Rule Check)
  • Synopsys Tool Chain

While the answer seems to obviously be yes in the case of standard logic cells, mvrc synopsys is less clear in the case of power management cells. This is because these functions, by design, are complex, and expected to vary with voltage dynamically.

Further, existing simulation models are represented in the Verilog language, which is inadequate to represent mixed-signal behavior. At this time, various standards have been mvrc synopsys to the address this issue, since the ability to write such functions is essential.

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The dynamic voltage-dependent behavior of these cells leads to another issue: There are new sets of timing arcs to be standardized in the first mvrc synopsys.

These need to be characterized for and exported in a standard library format.


While all of the prior discussion looks like it is primarily focused on static verification, consider the example earlier where the data pin has different properties compared to the isolation enable.

In this case, any assertions being written to compare the relative timing of these signals must be mvrc synopsys at the appropriate pins—this can be quite a task in a large design!


mvrc synopsys Retention cells represent another conundrum: Given the vast variance in retention schemes from one library element to another, how are these to be represented in a common format that yields to consistent representation?

Library vendors today have begun exporting retention cells with many new attributes and functions, which must be checked by both static and dynamic verification.

Changes on this front are primarily on the representation—the cells always had power and ground rails hooked up to them. One motivation mvrc synopsys include the power rails to the cells in the representation is the fact that they need to be explicitly hooked up to one of many rail networks and that connection must be verified.

Mvrc synopsys pdf files | rawmpsl | Scoo

mvrc synopsys Therefore, a verification process must independently infer power network connectivity from certain standard attributes.

The introduction of back-bias is another such additional item: The other factor is that delay and power characteristics of cells change with voltage. This means that multiple sets of library data may be needed and factored into the analysis of various design stages.


Simulation models need to now account for mvrc synopsys fact that the voltage applied to the cell could change: It is up to various simulation tools to impose voltage dependent behavior on these cell models beyond on and off.

These cells typically get connected to multiple power rails, without the notion mvrc synopsys a driving rail or primary supply.

Within these cells, the rails may actually drive different domains or be non-functional reference rails, such as a reference analog power supply.